Semiconductor memory device with reduced current consumption in data hold mode
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United States of America Patent
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Jul 30, 2002
Grant Date -
N/A
app pub date -
Feb 23, 2000
filing date -
Aug 5, 1999
priority date (Note) -
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Abstract
A power supply circuit generating a power supply voltage for refresh-related circuitry and a power supply circuit for column-related/peripheral control circuitry are controlled by a power supply control circuit to be put in different power supply voltage supplying states in a self refresh mode. In the self refresh mode, only self refresh-related circuitry receives a power supply voltage to perform refresh operation. A reduced current consumption can be achieved in the self refresh mode while fast access operation is not deteriorated.
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