Single stepping system and method for tightly coupled processors
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United States of America Patent
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Jul 23, 2002
Issued Date -
N/A
app pub date -
Jun 23, 1999
filing date -
Apr 24, 1997
priority date (Note) -
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Abstract
A method for controlling the execution of a sole target processor or a target processor embedded in a chain of target processor units by a host-processor. The target processor unit includes a shared control register, a shared memory accessible by both the target and host processor and a code memory alterable by the host processor and containing the target processor program. The shared control register includes a single step flag to indicate that the host processor is setting the single step mode of operation for the target processor. The shared control register further includes a clock inhibit flag to permit the target processor to stop execution. Clearing the clock inhibit flag releases the target processor to execute the program in the code memory during which the target processor tests the single step flag to determine whether it should stop execution after one instruction has been executed. If the flag is set the target processor reports its instruction pointer to the host processor via the shared memory and stops.
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