Three-dimensional memory array and method of fabrication
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United States of America Patent
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Jul 16, 2002
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app pub date -
Mar 21, 2001
filing date -
Apr 28, 2000
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Abstract
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.
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