Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer
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United States of America Patent
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Jul 9, 2002
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N/A
app pub date -
Jan 4, 1999
filing date -
Jan 4, 1999
priority date (Note) -
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Abstract
A method of forming a damascene structure in a semiconductor device arrangement uses a low k dielectric material in an etch stop layer that overlays a metal interconnect layer. The etch stop layer protects the metal interconnect layer, made of copper, for example, during the etching of a dielectric layer that overlays the etch stop layer. Following the etching of the dielectric layer, which stops on the etch stop layer, the etch stop layer is then etched with a chemistry that does not damage the underlying copper in the metal interconnect layer. The lower dielectric constant material employed in the etch stop layer reduces the overall dielectric constant of the film, thereby improving the operating performance of the chip.
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