Dynamic allocation of resources in multiple microprocessor pipelines
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United States of America Patent
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Jun 18, 2002
Grant Date -
Aug 23, 2001
app pub date -
Apr 26, 2001
filing date -
Apr 20, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A microprocessor having M parallel pipelines and N arithmetic logic units, where N is less than M. A single instruction fetch stage fetches multi-stage instructions, and a single instruction decoder provides a parallel set of three instructions to the three pipelines. The two ALUs are dynamically connected to two of the pipelines having instructions requiring an ALU, while the third pipeline executes an instruction in parallel that does not require an ALU. The third pipeline may have a move unit connected to it.
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