Circuit and method thereof for correcting over-erased flash memory cells
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United States of America Patent
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Jun 18, 2002
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N/A
app pub date -
Nov 15, 2001
filing date -
Apr 13, 2001
priority date (Note) -
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Abstract
A flash memory circuit has a flash memory array and a processor. The flash memory array has a plurality of erasable flash memory cells. Each of the flash memory cells is electrically connected to a corresponding bitline. If any over-erased flash memory cell exists in the flash memory array, a processor controls the flash memory circuit to apply a correction voltage to the bitline connected to the over-erased flash memory cell so as to correct the over-erased flash memory cell. The correction voltage is continuously applied until a current along the corresponding bitline drops below a predetermined value.
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