Test pattern for measuring variations of critical dimensions of wiring patterns formed in the fabrication of semiconductor devices
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United States of America Patent
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Jun 11, 2002
Grant Date -
N/A
app pub date -
Mar 2, 1999
filing date -
Mar 2, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A test pattern comprising a first region as an active region of a semiconductor device and a second region as a device isolation region around the first region. Formed on the second region of the substrate is a stepped layer having a different height from the first region. A plurality of parallel critical dimension bars are provided across the first and second regions. The stepped layer is an oxide layer formed at the same time when a device isolation oxide layer is formed on the chip region such that the test pattern according to the present invention has a similar configuration with the actual pattern on the chip region.
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