Variable duty cycle oscillator circuit with fixed minimum and maximum duty cycles
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United States of America Patent
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Jun 4, 2002
Grant Date -
N/A
app pub date -
May 10, 2000
filing date -
May 10, 2000
priority date (Note) -
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Abstract
An oscillator circuit includes an oscillation circuit producing a RAMP signal and at least two control signals STATE2 and STATE3, and a comparator comparing an externally produced error signal ERR with the RAMP signal. When the ERR signal is between minimum and maximum levels of the RAMP signal, the duty cycle of a PWMOUT signal of the oscillator circuit varies as a function of the difference between the ERR and RAMP signals, and preferably accounts for approximately 85% of the total period. When the ERR signal is less than or equal to the minimum level of the RAMP signal, the duty cycle of the PWMOUT signal is fixed at a first value which is preferably approximately 5% of the total duty cycle. When the ERR signal is greater than or equal to the maximum level of the RAMP signal, the duty cycle of the PWMOUT signal is fixed at a second value which is preferably approximately 90% of the total period. The three foregoing states of operation are established by the oscillation circuit as a function of the ratios of three capacitors relative to each other.
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