Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction
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United States of America Patent
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Jun 4, 2002
Issued Date -
N/A
app pub date -
Feb 29, 2000
filing date -
May 22, 1997
priority date (Note) -
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Abstract
At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.
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