Semiconductor memory device capable of high speed input/output of wide bandwidth data by improving usage efficiency of external data bus
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 28, 2002
Grant Date -
Nov 1, 2001
app pub date -
Dec 14, 1999
filing date -
Apr 16, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Serial write data of the burst length transmitted to a data bus are stored in parallel in latch circuits by a S/P data conversion circuit. In a memory cell array, one row of memory cells and four columns of memory cells are rendered active at the same time. Respective bit lines and latch circuits are connected by a sense amplifier I/O circuit. The write data of the burst length are written into the memory cell array at one time. The data of the bit length read out at one time from the memory cell array are converted into serial data by a P/S data conversion circuit to be transmitted to the data bus.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully