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Abstract

The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section. Thus, a transistor size can be determined while taking the diffusion sharing into consideration. In addition, unlike a conventional method, it is no longer necessary to repeatedly re-determine a transistor size and perform a compaction.

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First Claim