Cache memory employing dynamically controlled data array start timing and a microprocessor using the same
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United States of America Patent
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May 14, 2002
Issued Date -
N/A
app pub date -
Apr 25, 2000
filing date -
Jun 1, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.
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