Wafer-level packaging
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United States of America Patent
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-
May 14, 2002
Grant Date -
N/A
app pub date -
May 11, 2001
filing date -
Mar 22, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A wafer-level packaging process. A wafer having a plurality of bonding pads thereon exposed through a passivation layer formed on the wafer is provided, and an under bump metal (UBM) is formed on each bonding pad. A stress buffer layer is formed through which are formed a plurality of first openings that expose the under bump metals (UBM). Solder material is filled in the first openings of the stress buffer layer. Either a stencil or a patterned photoresist having a plurality of second openings is arranged on the stress buffer layer such that the second openings expose the first openings. A solder material is filled in the second openings. The solder material is reflowed, wherein if the stencil is used, it is removed before the reflow process while if the patterned photoresist is used, it is removed after the reflow process.
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