Stacked integrated circuit structure
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United States of America Patent
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-
Apr 30, 2002
Grant Date -
N/A
app pub date -
Oct 10, 2000
filing date -
Oct 10, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A stacked integrated circuit structure, in which main package bodies of a plurality of integrated circuits are stacked on each other. Connections between leads of the stacked integrated circuits are made by means of a stacking substrate. Therein, each of two surfaces of the stacking substrate has a plurality of terminals electrically connected to corresponding terminals. The stacking substrate includes a plurality of through vias as well, which connect to the corresponding terminals of the two surfaces. For two stacked integrated circuits, a hole can be defined in the stacking substrate, which housed the main package body of one of the two stacked integrated circuits, or by means of a plurality of separated substrates arranged around the perimeter of the main package body of one of the two stacked integrated circuits, so that the thickness of the stacked integrated circuits can be reduced.
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