Low power RAM memory cell using a precharge line pulse during write operation
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United States of America Patent
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Apr 30, 2002
Grant Date -
Jan 10, 2002
app pub date -
Nov 25, 1998
filing date -
Nov 28, 1997
priority date (Note) -
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Abstract
A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.
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