Wafer-level packaging process
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United States of America Patent
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-
Apr 23, 2002
Grant Date -
N/A
app pub date -
May 11, 2001
filing date -
Mar 22, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A wafer-level packaging process comprising: forming a patterned photoresist on a wafer covering a plurality of scribe lines and bump forming locations; forming a stress buffer layer on the regions not covered by the patterned photoresist; after removal of the patterned photoresist a plurality of first openings are defined in the stress buffer layer that also exposes the scribe lines; arranging either a stencil or a second patterned photoresist having a plurality of second openings over the wafer to cover the stress buffer layer and scribe lines, such that the second openings expose the first openings; filling a solder material in the openings; performing a reflow process, wherein according to the use of either the stencil or second photoresist, the reflow is respectively performed after or before the removal thereof. After dicing, the thus-packaged wafer can be directly connected onto an external carrier.
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