Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Apr 16, 2002
Grant Date -
N/A
app pub date -
Sep 22, 2000
filing date -
Sep 28, 1999
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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TOSHIBA MEMORY CORPORATION | 1-1 SHIBAURA 1-CHOME MINATO-KU TOKYO |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Shibata, Noboru | Yokohama, JP | 311 | 4902 |
# of filed Patents : 311 Total Citations : 4902 | |||
Takeuchi, Ken | Tokyo, JP | 169 | 6391 |
# of filed Patents : 169 Total Citations : 6391 | |||
Tanaka, Tomoharu | Yokohama, JP | 338 | 14532 |
# of filed Patents : 338 Total Citations : 14532 |
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Patent Citation Ranking
- 274 Citation Count
- G11C Class
- 97.57 % this patent is cited more than
- 23 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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