Parity determining apparatus and method
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Apr 9, 2002
Grant Date -
N/A
app pub date -
Aug 31, 2000
filing date -
Mar 24, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A parity determining circuit is used to determine the parity of a binary word. The binary word is represented by a sequence of optical bit slots. Each bit slot defines a respective one of two complementary logical states. The circuit includes: an input pulse stream generator that generates copies of the binary word; a combining device that receives two binary words, offsets one word with respect to the other, and then combines them to form a combination word; and a circuit that applies a copy of the original binary word together with the combination word to the combining device a number of times in succession. This results in a combination word that has a number of bits in the same logical state and that indicates the parity of the binary word.
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