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Abstract

A pipeline ADC includes an input stage and a first group of subsequent stages, wherein the input stage includes a unity gain amplifier having an input for receiving an analog input signal, an output, and first and second comparators each having a first input coupled to the output of the unity gain amplifier. The first comparator has a second input for receiving a first reference voltage an first output, and the second comparator has a second input for receiving a second reference voltage and an output. The input stage includes a full adder coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information. Each subsequent stage includes an amplifier of gain greater than 2 having an input and an output, a summer having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output, a switching circuit operating in response to the outputs of the first and second comparators of a previous stage to selectively couple one of a third reference voltage, a fourth reference voltage, and fifth reference voltage to a second input of the summer. Each subsequent stage also includes a full adder having a first input coupled to the first output, a second input coupled to the second output, the full adder producing bit information less significant than the MSB bit information. In the described embodiment, the third reference voltage is a negative reference voltage, the fourth reference voltage is a ground reference voltage, the fifth reference voltage is a positive reference voltage. The first reference voltage is midway between the third reference voltage and the ground reference voltage, and the second reference voltage is midway between the ground reference voltage and the fifth reference voltage. Each switching circuit operates to decode with three states represented by the first and second comparators of the previous stage. The plurality of stages include a second group of subsequent stages of lower binary bit significance than the first group of subsequent stages, the first group of subsequent stages being recursively self-calibrated, the second group of subsequent stages being not self-calibrated. The pipeline ADC is included in a self-calibrating pipeline ADC including a plurality of analog-to-digital conversion units and a recursive calibrating section operable for calibrating errors associated with an immediately preceding first conversion unit.

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