Importance

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Abstract

This invention provides a logic block comprising an mxn array of partial calculating circuits (where m.gtoreq.2 and n.gtoreq.2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.

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First Claim