High speed semiconductor memory device with short word line switching time

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6366507
SERIAL NO

09653900

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Abstract

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Setting means (such as fuse circuits) for adjusting the timings of various signals such as an activation timing of a sense amplifier, a fall timing of a word line, a recovery operation (equalization) of a bit lines and so forth, checking an operation in a test stage of a chip, and permanently programming (fixing) the timing of an internal signal to the condition of the highest operation speed that can be confirmed as acquirable in this check stage, is provided.

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VACHELLIA LLC500 NEWPORT CENTER DRIVE 7TH FLOOR NEWPORT BEACH CA 92660

International Classification(s)

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  • 2000 Application Filing Year
  • G11C Class
  • 2416 Applications Filed
  • 1639 Patents Issued To-Date
  • 67.84 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2000200120022003200420052006200720080255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akioka, Takashi Akishima, JP 40 637
Shinozaki, Masao Higashimurayama, JP 24 328

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Patent Citation Ranking

  • 9 Citation Count
  • G11C Class
  • 2.28 % this patent is cited more than
  • 23 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges1524617092412623139531601 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +020406080100120140160180200220240260

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