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Abstract

A clock splitter circuit for providing a Single Event Upset (SEU) tolerant clock signals to latches in a space-based environment. The splitter circuit includes an event offset delay. The event offset delay receives an undelayed clock signal and generates an undelayed inverted clock, a delayed clock signal and an inverted delayed clock signal. The delayed clock signal and the inverted delayed clock signal are delayed by the known duration of Single Event Effects (SEE) on logic. The delayed and undelayed clock signals are passed to a pair of event blocking filters which block any disturbance in the undelayed and/or undelayed clock signals. The event blocking filters each generate a pair of in-phase inverted output signals. The event blocking filters are designed such that both pairs of outputs may not be low simultaneously. The in-phase output signals from each event blocking filter drive an inverting clock driver to provide a pair of SEU tolerant non-overlapping clock driver phase output signals to one or more latches.

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First Claim