FSK demodulator
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United States of America Patent
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Mar 19, 2002
Grant Date -
N/A
app pub date -
Jul 6, 1998
filing date -
Oct 9, 1997
priority date (Note) -
Expired
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Abstract
A 4-level direct conversion receiver demodulator 1 comprises an edge detector 2, a finite impulse response filter 3, an N-bit path 4, a data slicer 5 and automatic frequency control device 6. The edge detector 2 receives Limited I (LIMI) and Limited Q (LIMQ) signals on respective ones of first and second input leads 7 and 8 from a direct conversion receiver arrangement R. The edge detector 2 contains logic to provide an EDGE signal, comprising a short pulse when any edge is detected in either of the LIMI and LIMQ signals, on a line 9 and an I Lead Q (ILQ) signal, indicative of which of the LIMI and LIMQ signals has the leading phase, on a line 10 to the filter 3. The edge detector 2 thus determines both the frequency and the relative phase of the signals provided by the limited output direct conversion receiver R without the use of analogue to digital conversion circuitry. The N-bit path output 4 from the filter 3 is provided to both the data slicer 5 and to the AFC device 6. A demodulated output signal is provided in the form of an MSB and an LSB on respective ones of demodulator outputs 11 and 12.
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