Semiconductor memory device that can access two regions alternately at high speed
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United States of America Patent
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Mar 19, 2002
Grant Date -
N/A
app pub date -
Jan 16, 2001
filing date -
Jul 18, 2000
priority date (Note) -
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Abstract
A latch is provided corresponding to each column. The data read out onto a bit line pair can be copied to the latch circuit when a signal TG is driven to an H level. Since data read out from the latch does not require row addressing, data can be read out from a particular column address by rendering a latch select line active even in the case where a word line corresponding to another row address is active. A semiconductor memory device that is not reduced in the effective transfer rate can be provided even in the case where alternate access is effected starting continuously from two different row addresses in the same bank.
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