System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
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United States of America Patent
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Mar 12, 2002
Grant Date -
N/A
app pub date -
Jul 25, 2000
filing date -
Jul 25, 2000
priority date (Note) -
Expired
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Abstract
A cache coherency directory for a shared memory multiprocessor computer system. A data structure is associated with each cacheable memory location, the data structure comprising locations for storing state values indicating an exclusive state, a shared state, an uncached state, a busy state, a busy uncached state, a locked state, and a pending state. The busy state and pending state cooperate to reserve a cache line for future use by a processor while the cache line is currently being used by one or more other processors.
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