Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port
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United States of America Patent
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Mar 12, 2002
Issued Date -
N/A
app pub date -
Nov 9, 2000
filing date -
Oct 29, 1997
priority date (Note) -
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Abstract
There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.
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