Method and apparatus for partial-scan built-in self test logic

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United States of America Patent

PATENT NO 6349398
SERIAL NO

09237486

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Abstract

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An integrated circuit apparatus includes main logic for performing digital logic operations. The main logic is further comprised of a plurality of logic modules, each having at least one logic block associated with the logic module. Many times several logic blocks are associated with the logic modules. The main logic further also includes a number of input pins for receiving data and a number of output pins for outputting data from the main logic. Also included on the integrated circuit apparatus is testing logic for performing dynamic tests of the main logic. The testing logic further includes a first type of built-in testing logic for testing a first number of the logic modules of the main logic and a second type of built-in test logic for testing a second number of logic blocks. The second number of logic blocks connected to the second type of built-in scan logic are generally untestable using the first type of built-in logic. The second type of testing logic includes a test data input for inputting test data to the second type of testing logic and to the input pins of the main logic, and a test data output for outputting test data from the second type of testing logic and from the main logic. The second type of built-in scan logic Includes an internal scan ring. The testing logic also includes a command register for receiving commands and outputting control signals to control the main logic and the testing logic.

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Patent Owner(s)

Patent OwnerAddress
RPX CORPORATIONFOUR EMBARCADERO SUITE 4000 SAN FRANCISCO CA 94111

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Resnick, David Eau Claire, WI 25 679

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