Method of operating flash memory
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United States of America Patent
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Feb 12, 2002
Issued Date -
N/A
app pub date -
Feb 1, 2000
filing date -
May 30, 1996
priority date (Note) -
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Abstract
A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential no more negative than 6.5 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential no more positive than 8.0 volts.
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