Process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity
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United States of America Patent
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Jan 22, 2002
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N/A
app pub date -
Nov 30, 1998
filing date -
Sep 12, 1994
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Abstract
A process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity of charge carriers within a silicon wafer includes forming a plurality of semiconductor zones in the surface; reducing surface recombination velocity of charge carriers within the silicon wafer by maintaining temperature below 100.degree. C. while sequentially performing the steps of cleaning the surface to remove oxide; drying the surface by blowing a non-oxidizing gas thereon; directly applying a layer of lacquer onto the surface at a temperature below 100.degree. C.; and drying the layer of lacquer at a temperature below 100.degree. C. to generate an electrically non-conducting layer and reduce the surface recombination velocity of charge carriers within the silicon wafer in which the layer of lacquer contains halogen in a concentration of more than 0.1 volume %; and forming at least one conducting structure on the surface of the layer of lacquer.
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