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Abstract

A clock synchronization method, for use in generating a system clock of a predetermined frequency with reference to a reference clock, receives the reference clock, the system clock and a divided clock having a same frequency as that of the reference clock, wherein the divided clock is obtained by dividing the system clock by a predetermined integer. Phase deviations between the reference clock and the divided clock are obtained, wherein a phase deviation is the number of periods of the system clock in a section between a rising edge of the reference clock and a nearest rising edge of the divided clock. Consecutive phase deviations are averaged to thereby generate an average phase deviation of a 3rd order, wherein the number of averaged consecutive phase deviations varies according to phase jitter characteristics of the reference clock. And, the frequency of the system clock is controlled based on the average phase deviation of the 3rd order.

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First Claim