Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
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United States of America Patent
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Jan 8, 2002
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N/A
app pub date -
Mar 18, 1999
filing date -
Jun 10, 1998
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Abstract
A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.
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