DSP coprocessor having control flags mapped to a dual port section of memory for communicating with the host
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United States of America Patent
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-
Dec 25, 2001
Grant Date -
N/A
app pub date -
Jan 27, 1999
filing date -
Sep 23, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A DSP coprocessor 2 is connected to a host sub-system (3). The host sub-system (3) has a host processor (4), a host RAM (5), and shared RAM banks (6, 7). Multiplexers (11) provide access for either the DSP or the host to a shared RAM bank. Macro commands for functions of the DSP coprocessor are retrieved from the shared RAM banks. This allows comprehensive interaction of the host and the DSP coprocessor.
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