Atomic-level electronic network and method of fabrication

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United States of America Patent

PATENT NO 6331454
SERIAL NO

09247884

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Abstract

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An insulated lattice is prepared with a plurality of lattice oriented atoms to create a substantially planar surface having a lattice arrangement. Any unsatisfied chemical bonds are terminated along the substantially planar surface by placing atoms at the site of the unsatisfied chemical bonds to terminate the unsatisfied chemical bonds and insulate the surface to form a platform. In one aspect of the invention, the insulator atoms are removed at predetermined locations. Atoms to form the atomic chain are placed at predetermined locations on the insulated lattice platform to form a first atomic chain which behaves as one of a conductor, a semiconductor and an insulator. A second atomic chain is also placed at predetermined locations on the insulated lattice platform so that the second chain behaves as another of a conductor, a semiconductor and an insulator. These placements are made such that the second atomic chain is electrically coupled to the first atomic chain, and the second atomic chain behaves differently than the first atomic chain. That is, in the first chain the atoms are placed at a first separation distance and in the second chain the atoms are placed at a second separation distance, where the second separation distance is different than the first.

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Patent Owner(s)

Patent OwnerAddress
BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY1705 EL CAMINO REAL PALO ALTO CA 94306-1106
RESEARCH DEVELOPMENT CORP OF JAPANTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Dehuan Palo Alto, CA 7 16
Takiguchi, Yoshihiro Tokyo, JP 32 206
Yamada, Toshishige Mountain View, CA 2 7
Yamamoto, Yoshihisa Stanford, CA 153 2055

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