Parallel access virtual channel memory system
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United States of America Patent
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Dec 4, 2001
Issued Date -
N/A
app pub date -
Nov 10, 1999
filing date -
Nov 18, 1996
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Abstract
A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include, interfaces, cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is independently addressable, such that particular memory masters can be assigned to access particular virtual access channels.
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