Synchronous semiconductor memory device having improved operational frequency margin at data input/output
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United States of America Patent
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Nov 27, 2001
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N/A
app pub date -
Mar 12, 1999
filing date -
Jun 17, 1998
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Abstract
A synchronous semiconductor memory device includes a latch for temporarily storing data to be output to the outside, and a latch temporarily storing data input from the outside. The latches operate based on an internal clock when exchanging data with internal memory block, and operate based on a clock in phase with an external clock when exchanging data with the outside.
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