Semiconductor memory array with buried drain lines and processing methods therefor
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United States of America Patent
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Nov 27, 2001
Grant Date -
N/A
app pub date -
May 10, 1999
filing date -
Nov 24, 1997
priority date (Note) -
Expired
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Abstract
A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated region formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.
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