Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers
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United States of America Patent
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Nov 20, 2001
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N/A
app pub date -
May 14, 1999
filing date -
May 14, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A write buffer unit operates in a cached memory microprocessor system by dynamically reconfigurable timed flushing of a queue of coalescing write buffers in the unit. Each time an additional one of the coalescing write buffers is allocated, a time-out period is generated which is inversely related to the number of allocated write buffers. After one of the allocated write buffers times out by exceeding the time-out period with no write activity to the coalescing write buffer, a controller in the unit determines the least recently written to allocated write buffer, and generates control signals to flush that write buffer.
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