Semiconductor memory device with a plurality of memory blocks
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Nov 6, 2001
Grant Date -
N/A
app pub date -
Sep 25, 2000
filing date -
Apr 12, 2000
priority date (Note) -
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Abstract
In accordance with the present invention a semiconductor memory device includes a connection control circuit controlling a connection between a bit line pair and a data input/output line pair. The connection control circuit includes a flip flop. The connection control circuit responds to a sense amplifier activation signal and a column bank address by setting a level of an interlock signal controlling a gate for electrically connecting the bit line pair and the data input/output line pair together.
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