Mechanism to simplify built-in self test of a control store unit
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United States of America Patent
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Oct 30, 2001
Grant Date -
N/A
app pub date -
Feb 17, 1999
filing date -
Feb 17, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A control store unit having a control store address generator able to provide both the normal control store address generation functions, and the BIST/logout address generation functions. In response to a test enable signal, the address generator switches between two modes: a normal mode and a test mode. Under the normal mode, normal control store addresses are generated. Under the test mode, a sequence of BIST/logout addresses are generated that sequentially cycles through the entire control store memory at full CPU speed.
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