Pipeline processing apparatus for reducing delays in the performance of processing operations
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United States of America Patent
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-
Oct 23, 2001
Issued Date -
N/A
app pub date -
Oct 29, 1999
filing date -
Oct 4, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A decoder decodes a branch instruction. An operating section executes logical, arithmetic, and shift operations. A register file store operation result of the operating section. A program counter counting the address of the present programs. A direct-setting bus is provided to allowing the decoder to directly set an immediate value to the program counter without passing through an output bus of the operating section. And, a switch selectively connects the direct-setting bus or the output bus to the program counter.
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