Microcomputer having data execution units mounted thereon
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 16, 2001
Grant Date -
N/A
app pub date -
Dec 15, 1998
filing date -
Dec 17, 1997
priority date (Note) -
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Abstract
A microcomputer for feeding source data necessary for operations without any delay while retaining the consistency on instruction lines between the ordinary single operations and the SIMD (Single Instruction Multiple Data) type parallel operations. The microcomputer comprises: a first memory and a second memory adapted to be individually fed with a common address from the address generating unit; a first execution unit coupled to the first memory and the second memory; and a second execution unit coupled to the first memory and the second memory. The second execution unit is mounted together with the central processing unit, the first memory, the second memory and the first execution unit on a common semiconductor substrate. The microcomputer is provided with: a first operating mode, in which data are fed from one of the first and second memories to the first execution unit and in which the first execution unit executes the operations whereas the second execution unit interrupts the operations; and a second operating mode, in which the data are fed from the first memory to the first execution unit and fed from the second memory to the second execution unit and in which the first execution unit and the second execution unit execute the operations.
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