Method and apparatus for performing latency based hazard detection
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United States of America Patent
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Oct 16, 2001
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N/A
app pub date -
Dec 30, 1998
filing date -
Dec 30, 1998
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Abstract
Performing hazard detection in a processor that exhibits register latencies between execution units. The opcode classes of producer and consumer instructions are determined. Using these opcode classes, the register latency between the producer and consumer instructions is determined, and a register status signal is sent.
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