Semiconductor memory device capable of suppressing degradation in operation speed after replacement with redundant memory cell
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United States of America Patent
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Oct 16, 2001
Grant Date -
N/A
app pub date -
Jun 8, 2000
filing date -
Dec 27, 1999
priority date (Note) -
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Abstract
A row predecoder receives internal address signals output from address latch circuits and outputs the predecode signals. A spare determination circuit receives address signals and outputs a comparison result with a defective row address stored in advance. A normal row decoder receives a predecode address signal and selects a word line within a corresponding normal memory cell block when a redundancy replacement is not performed, while a redundant row decoder receives a predecode signal and selects a redundant word line within a redundant memory cell block when the redundancy replacement is performed.
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