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Abstract

The invention provides a NAND type nonvolatile memory comprising: a sense circuit 100 having a constant current supply source P7 connected to a bit line to which memory cells are connected and a sense transistor N8 for sensing potential at the connection point thereof; a first reference potential ARVss on the opposite side from the bit line of the memory cells; and a second reference potential PBVss to which the source of the sense transistor is connected, wherein during Erase-verify operations the first reference potential ARVss and the second reference potential PBVss are controlled to predetermined positive potential. By controlling the first reference potential ARVss to positive potential, the control gate level of a memory cell can be equivalently brought to Erase-verify level (which is negative), and by further controlling the second reference potential PBVss of the sense transistor N8 to positive potential as well, the equivalent threshold voltage of the sense transistor N8 can be increased, or the equivalent trip level of the sense inverter increased, thereby solving the conventional problems associated with Erase-verify operations.

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First Claim