Method and apparatus for hardening a static random access memory cell from single event upsets
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United States of America Patent
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Sep 4, 2001
Grant Date -
N/A
app pub date -
Nov 17, 1999
filing date -
May 28, 1999
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Abstract
A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
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