Semiconductor memory device
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United States of America Patent
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Aug 7, 2001
Issued Date -
N/A
app pub date -
Oct 9, 1998
filing date -
Oct 14, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.
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