High density memory structure
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United States of America Patent
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Aug 7, 2001
Issued Date -
N/A
app pub date -
Jan 14, 1998
filing date -
Aug 4, 1995
priority date (Note) -
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Abstract
A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.
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