Method for fabricating an oxide layer on silicon with carbon ions introduced at the silicon/oxide interface in order to reduce hot carrier effects
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United States of America Patent
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Jul 31, 2001
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N/A
app pub date -
Dec 30, 1999
filing date -
Dec 30, 1999
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Abstract
A fabrication method for an oxide layer with reduced interface-trapped charges, which is applicable to the fabrication of a gate oxide layer of a flash memory device, is described. The method includes conducting a first inert ambient annealing process, followed by growing an oxide layer on the silicon substrate. A second inert ambient annealing process is then conducted on the oxide layer. Carbon ions are then incorporated into the interface between the oxide layer and the silicon substrate, followed by a third ambient annealing process.
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