Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 24, 2001
Grant Date -
N/A
app pub date -
Dec 14, 1998
filing date -
Dec 14, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A vector-processor SIMD RISC computer system uses virtual addressing and overlapped instruction execution. Indicators for each of the architected registers assume different states when an instruction, overlapped with a vector memory-reference instruction, has or has not read from or written to a particular register. Multiple overlapped vector memory-reference instructions are assigned separate sets of indicators. Indicators in a certain state prevents a subsequent overlapped instruction from writing to its associated register.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully