Cache or TLB using a working and auxiliary memory with valid/invalid data field, status field, settable restricted access and a data entry counter
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United States of America Patent
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Jul 10, 2001
Grant Date -
N/A
app pub date -
Nov 8, 1996
filing date -
May 11, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The memory device includes an auxiliary memory and a useful memory. Both memories are provided with a plurality of memory entries. The auxiliary memory is intended for storing regions of an address space therein. This includes a plurality of addresses with which the useful memory may be addressed. A write/read access to a useful memory entry is not possible if a status field associated with the useful memory entry signals a restricting status and the address with which the useful memory entry is addressed lies within at least one of the address space regions stored in the auxiliary memory. Efficient region-selective flushing of the useful memory is possible with this procedure.
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